TM4C1236H6PM Datasheet, PDF (298/1236 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 41: Watchdog Timer Software Reset (SRWD), offset 0x500
The SRWD register provides software the capability to reset the available watchdog modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the watchdog modules and has the same bit polarity as the corresponding SRCRn
bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRWD register. While the SRWD bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRWD bit.
There may be latency from the clearing of the SRWD bit to when the peripheral is ready for use.
Software can check the corresponding PRWD bit to be sure.
Important: This register should be used to reset the watchdog modules. To support legacy software,
the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR0 register can
be read back correctly when reading the SRCR0 register. If software uses this register
to reset a legacy peripheral (such as Watchdog 1), the write causes proper operation,
but the value of that bit is not reflected in the SRCR0 register. If software uses both
legacy and peripheral-specific register accesses, the peripheral-specific registers must
be accessed by read-modify-write operations that affect only peripherals that are not
present in the legacy registers. In this manner, both the peripheral-specific and legacy
registers have coherent information.
Watchdog Timer Software Reset (SRWD)
Base 0x400F.E000
Offset 0x500
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
R1
R0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
R1
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer 1 Software Reset
Value Description
0 Watchdog module 1 is not reset.
1 Watchdog module 1 is reset.
298
June 12, 2014
Texas Instruments-Production Data