AM3359_1211 Datasheet, PDF (83/222 Pages) Texas Instruments – AM335x ARM Cortex-A8 Microprocessors (MPUs)

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SPRS717D – OCTOBER 2011 – REVISED MAY 2012
3.3 DC Electrical Characteristics
Table 3-7 summarizes the dc electrical characteristics.
Note: The interfaces or signals described in Table 3-7 correspond to the interfaces or signals available in
multiplexing mode 0. All interfaces or signals multiplexed on the terminals described in Table 3-7 have the same
dc electrical characteristics.
Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted)
PARAMETER
MIN
NOM
MAX UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(mDDR - LVCMOS mode)
V_IH
High-level input voltage
0.65 *
VDDS_DDR
V
V_IL
Low-level input voltage
0.35 *
VDDS_DDR
V
V_HYS
V_OH
Hysteresis voltage at an input
High level output voltage, driver enabled, pullup
or pulldown disbaled
I_OH = 8 mA
0.07
VDDS_DDR -
0.4
0.25 V
V
V_OL
Low level output voltage, driver enabled, pullup
or pulldown disbaled
I_OL = 8 mA
0.4 V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
I_I
Input leakage current, Receiver disabled, pullup enabled
-240
10
-80 ^µA
Input leakage current, Receiver disabled, pulldown enabled
80
240
Total leakage current through the terminal connection of a
I_OZ
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
10 µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(DDR2 - SSTL mode)
V_IH
High-level input voltage
DDR_VREF +
V
0.125
V_IL
Low-level input voltage
DDR_VREF - V
0.125
V_HYS
Hysteresis voltage at an input
NA
V
V_OH
High-level output voltage, driver enabled, pullup I_OH = 8 mA
VDDS_DDR -
V
or pulldown disbaled
0.4
V_OL
Low-level output voltage, driver enabled, pullup I_OL = 8 mA
or pulldown disbaled
0.4 V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
I_I
Input leakage current, Receiver disabled, pullup enabled
-240
10
-80 ^µA
Input leakage current, Receiver disabled, pulldown enabled
80
240
I_OZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
10 µA
Copyright © 2011–2012, Texas Instruments Incorporated
Device Operating Conditions
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