AM3359_1211 Datasheet, PDF (169/222 Pages) Texas Instruments – AM335x ARM Cortex-A8 Microprocessors (MPUs)

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SPRS717D – OCTOBER 2011 – REVISED MAY 2012
Table 5-59. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK/DDR_CKn
DQS0
DDR_DQS0/DDR_DQSn0
DQS1
DDR_DQS1/DDR_DQSn1
SIGNAL NET CLASS
ADDR_CTRL
DQ0
DQ1
Table 5-60. Signal Net Class Definitions
ASSOCIATED CLOCK
NET CLASS
CK
DQS0
DQS1
AM335x PIN NAMES
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
5.5.2.3.3.9 DDR3 Signal Termination
Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations
(ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are
covered in the routing rules in the following sections.
5.5.2.3.3.10 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x
device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with
a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide
trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to
accommodate routing congestion.
5.5.2.3.3.11 VTT
Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike
DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the
ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should
be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.
5.5.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 5-61.
5.5.2.3.4.1 Two DDR3 Devices
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as
one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a
pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
5.5.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 5-47 shows the topology of the CK net classes and Figure 5-48 shows the topology for the
corresponding ADDR_CTRL net classes.
Copyright © 2011–2012, Texas Instruments Incorporated
Peripheral Information and Timings 169
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