TMS320C6713B_17 Datasheet, PDF (80/154 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
PLL and PLL controller (continued)
Table 36. PLL Control/Status Register (PLLCSR) [0x01B7 C100]
31
28 27
24 23
20 19
Reserved
R−0
15
12 11
87
6
5
4
3
Reserved
R−0
STABLE
R−x
Reserved
R−0
PLLRST
RW−1
Legend: R = Read only, R/W = Read/Write; -n = value after reset
2
Reserved
R/W−0
1
PLLPWRDN
R/W−0b
16
0
PLLEN
RW−0
BIT #
31:7
6
5:4
3
2
1
0
Table 37. PLL Control/Status Register (PLLCSR) Description
NAME
Reserved
STABLE
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
DESCRIPTION
Reserved. Read-only, writes have no effect.
Clock Input Stable. This bit indicates if the clock input has stabilized.
0 – Clock input not yet stable. Clock counter is not finished counting (default).
1 – Clock input stable.
Reserved. Read-only, writes have no effect.
Asserts RESET to PLL
0 – PLL Reset Released.
1 – PLL Reset Asserted (default).
Reserved. The user must write a “0” to this bit.
Select PLL Power Down
0 – PLL Operational (default).
1 – PLL Placed in Power-Down State.
PLL Mode Enable
0 – Bypass Mode (default). PLL disabled.
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
directly from input reference clock.
1 – PLL Enabled.
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
from PLL output.
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