TMS320C6713B_17 Datasheet, PDF (37/154 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
DEVICE CONFIGURATIONS (CONTINUED)
Table 22. Peripheral Pin Selection Matrix^†
SELECTION BITS
PERIPHERAL PINS AVAILABILITY
B
B
G
I
T
I
T
M
c
A
N
A
M
V
A
S
P
L
0‡
E
U
E
M
c
A
S
P
1
M
M
I
I
c
c
2
2
B
B
C
C
S
S
0
1
P
P
T
I
M
E
R
0
1
0
T
P
I
I
M
H
O
E
P
R
I
P
I
1
N
S
E
M
I
F
0
HPI_EN
(boot config
pin)
AHCLKX1
AHCLKR1
ACLKX1
ACLKR1
AFSX1
AFSR1
AMUTE1
AXR1[0] to
AXR1[7]
GP[0:1],
GP[3],
GP[8:15]
None
Plus:
GP[2]
ctrl’d by
GP2EN
bit
1
None
NO
All
GP[0:1],
GP[3],
GP[8:15]
0 None
All
ACLKX0
ACLKR0
MCBSP0DIS
AFSX0
(DEVCFG bit) _{1 AFSR0}
AHCLKR0
AXR0[0]
AXR0[1]
None
NO
AMUTE0
0 AXR0[5]
MCBSP1DIS
(DEVCFG bit)
AXR0[6]
AXR0[7]
AMUTE0
1
AXR0[5]
AXR0[6]
AXR0[7]
None
All
All
None
TOUT0SEL
NO
0 _AXR0[2]
(DEVCFG bit)
1 AXR0[2]
TOUT0
NO
TOUT0
TOUT1SEL
0
NO
AXR0[4]
(DEVCFG bit)
1 AXR0[4]
TOUT1
NO
TOUT1
0
HD12 (boot
config pin) ^§
1
ED[7:0];
HD8 = 1/0
ED[7:0] side
[HD8 = 1 (Little)]
ED[31:24] side
[HD8 = 0 (Big)]
† _{Gray blocks indicate that the peripheral is not affected by the selection bit.}
‡ _{The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 23 for more detailed}
information.
§ _{For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness portion of this data sheet.}
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