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TIBPLS506AC Datasheet, PDF (8/16 Pages) Texas Instruments – 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
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TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
glossary — timing model
tpd(1) — Maximum time interval from the time a signal edge is received at any input pin to the time any logically
affected combinational output pin delivers a response.
tpd(2) — Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin
corresponding to any output SR register.
tpd(3) — Maximum time interval from the positive edge on the clock input pin to the response on any logically
affected combinational configured output (at the pin), where data origin is any internal SR register.
tpd(b) — Maximum time interval from the time a signal edge is received at any input pin to the time any logically
affected combinational output pin delivers a response, where data passes through a C-array once
before reaching the affected output.
tpd(c) — Maximum time interval from the positive edge on the clock input pin to the response on any logically
affected combinational configured output (at the pin), where data origin is any internal SR register
and data passes once through a C-array before reaching an affected output.
tsu(1) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects the S or R line of any output SR register.
tsu(2) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects the S or R line of any internal SR register.
tsu(a) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data passes once through a C-array before reaching
an affected S or R line on any internal SR register.
tsu(b) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data passes once through a C-array before reaching
an affected S or R line on any output SR register.
tmin(1) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register or counter bit to feed the S or R line of any output SR register.
tmin(2) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register.
tmin(3) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register and data
passes once through a C-array before reaching an affected S or R line on any internal SR register.
tmin(c) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any output SR register and data
passes once through a C-array before reaching an affected S or R line on any output SR register.
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