TIBPLS506AC Datasheet, PDF (6/16 Pages) Texas Instruments – 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER

TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
fmax‡
tpd
FROM
(INPUT)
TO
(OUTPUT)
Without C-array
With C-array
External feedback without C-array
External feedback with C-array
Q (nonregistered)
CLK
Q (registered)
I or Feedback
Q (nonregistered)
TEST CONDITION
R1 = 300 Ω,
R2 = 390 Ω,
See Figure 5
MIN TYP† MAX UNIT
58
65
33
45
45
60
MHz
28.5
40
6
25
ns
3
10
6
20 ns
ten
OE↓
Q
tdis
OE↑
Q
† _{All typical values are at VCC = 5 V, TA = 25°C.}
‡ _{See the fmax calculations section.}
1
6
10 ns
1
6
10 ns
f_max calculations
The following is a brief description of how the different operating frequencies can be achieved when using the
TIBPLS506A.
) ^{fmax without C-(complementary) array =} tsu
1
tpd
CLK to Qwhere ^{setup time tsu before CLK at the S/R}
register inputs = 12 ns and propagation delay time t_pd CLK to Q for the internal S/R registers = 5ns (difference
in t_pd from CLK and feedback, 25 to 20).
+ + + ^{Thus: f}max ^{for this condition}
1
(12 + 5) ns
1
17 ns
58 MHz.
) ^{fmax with the C-array =} tsu
1
tpd
CLK to Qwhere
t_su
setup
time
before
CLK
at
the
S/R
register
inputs = 25 ns and propagation delay time t_pd CLK to Q for the internal S/R registers = 5 ns (difference in t_pd
from CLK and feedback, 25 to 20)
+ + + ^{Thus: f}max ^{for this condition}
1
(25 + 5) ns
1
30 ns
33 MHz.
) ^{fmax external feedback without the C-array =} tsu
1
tpd
CLK to Qwhere ^{setup time tsu before CLK at the}
S/R register inputs = 12 ns and propagation delay time t_pd CLK to Q for the internal S/R registers = 10 ns
+ + + ^{Thus: f}max ^{for this condition}
1
(12 + 10) ns
1
22 ns
45 MHz.
) ^{fmax external feedback with the C-array =} tsu
1
tpd
CLK to Qwhere ^{setup time tsu before CLK at the S/R}
register inputs = 25 ns and propagation delay time t_pd CLK to Q for the internal S/R registers = 10 ns.
+ + + ^{Thus: f}max ^{for this condition}
1
(25 + 10) ns
1
35 ns
28.5 MHz.
6
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