LMC6953 Datasheet, PDF (8/19 Pages) National Semiconductor (TI) – PCI Local Bus Power Supervisor

LMC6953
SNVS132D – APRIL 1998 – REVISED APRIL 2013
BLOCK DIAGRAM OF THE LMC6953
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** All five comparators' positive power supplies are connected to V_DD
Power Failure
Fail
X
X
X
X
X
OK
5V Over-Voltage
X
Fail
X
X
X
X
OK
TRUTH TABLE⁽¹⁾
5V Under-Voltage 3.3V Over-Voltage
X
X
X
X
Fail
X
X
Fail
X
X
X
X
OK
OK
(1) X = Don't Care
3.3V Under-Voltage
X
X
X
X
Fail
X
OK
MR
High
High
High
High
High
Low
High
RESET
Low
Low
Low
Low
Low
Low
High
PIN DESCRIPTION
Pin
Name
Function
1
V_DD
5V input supply voltage. This pin supplies power to the internal comparators. It can be connected to a capacitor
acting as a back-up battery. Otherwise, it should be shorted to the 5V pin.
2
5V
5V input supply voltage. This pin is not connected to the positive power supply of the internal comparators. It
provides input signal to the 5V window comparators as well as the power failure comparator.
3
3.3V
3.3V input supply voltage. This pin provides input signal to the 3.3V window comparators and the power failure
comparator.
4
MR
Manual reset input pin. It takes 5V CMOS logic low and triggers RESET . If not used, this pin should be connected to
V_DD.
5 PWR―GND Ground.
6
GND
This pin should be grounded at all times.
7
RESET Active low reset output. RESET holds low for 100 ms after both 5V and 3.3V powers recover, or after manual reset
signal returns to high state.
8
C_EXT
External capacitor pin. The value of C_EXT sets the reset delay.
8
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