DS92LV090AEP Datasheet, PDF (8/14 Pages) Texas Instruments – DS92LV090AEP 9 Channel Bus LVDS Transceiver

Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-903, AN-971,
AN-977, and AN-1108.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recommended
practices are:
• Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS port
side) connector as possible.
• Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Two or three high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel
should be used between each V_CC and ground. The
capacitors should be as close as possible to the V_CC pin.
Multiple vias should be used to connect V_CC and Ground
planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors
should be used.
• Use the termination resistor which best matches the
differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• Use controlled impedance media. The backplane and
connectors should have a matched differential
impedance.
Test Circuits and Timing Waveforms
TABLE 1. Functional Table
MODE SELECTED
DE
RE
DRIVER MODE
H
H
RECEIVER MODE
L
L
TRI-STATE MODE
L
H
LOOP BACK MODE
H
L
TABLE 2. Transmitter Mode
INPUTS
OUTPUTS
DE
D_IN
DO+ DO−
H
L
L
H
H
H
H
L
H
0.8V< D_IN <2.0V
X
X
L
X
Z
Z
TABLE 3. Receiver Mode
INPUTS
RE
(RI+) – (RI−)
L
L (< −100 mV)
L
H (> +100 mV)
L
−100 mV < V_ID < +100 mV
H
X
X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
OUTPUT
L
H
X
Z
FIGURE 1. Differential Driver DC Test Circuit
20119503
20119504
FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit
7
201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19
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