DS92LV090AEP Datasheet, PDF (7/14 Pages) Texas Instruments – DS92LV090AEP 9 Channel Bus LVDS Transceiver

AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 9, 17)
Symbol
Parameter
Conditions
Min Typ
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t_PHLD
Differential Prop. Delay High to Low (Note 11)
t_PLHD
Differential Prop. Delay Low to High (Note 11)
t_SKD1
Differential Skew |t_PHLD–t_PLHD| (Note 12)
t_SKD2
Chip to Chip Skew (Note 15)
t_SKD3
Channel to Channel Skew (Note 16)
t_TLH
Transition Time Low to High
t_THL
Transition Time High to Low
t_PHZ
Disable Time High to Z
t_PLZ
Disable Time Low to Z
t_PZH
Enable Time Z to High
t_PZL
Enable Time Z to Low
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t_PHLD
t_PLHD
t_SDK1
t_SDK2
t_SDK3
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
Differential Prop. Delay High to Low (Note 11)
Differential Prop Delay Low to High (Note 11)
Differential Skew |t_PHLD–t_PLHD| (Note 12)
Chip to Chip Skew (Note 15)
Channel to Channel Skew (Note 16)
Transition Time Low to High
Transition Time High to Low
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
R_L = 27Ω,
Figures 2, 3,
C_L = 10 pF
R_L = 27Ω,
Figures 4, 5,
C_L = 10 pF
Figures 6, 7,
C_L = 35 pF
R_L = 500Ω,
Figures 8, 9,
C_L = 35 pF
0.6
1.4
0.6
1.4
80
0.25
0.6
0.5
3
3
3
3
1.6
2.4
1.6
2.4
80
0.35
1.5
1.5
4.5
3.5
3.5
3.5
Unit
Max
s
2.2 ns
2.2 ns
ps
1.6 ns
0.45 ns
1.2 ns
1.2 ns
8
ns
8
ns
8
ns
8
ns
3.2 ns
3.2 ns
ps
1.6 ns
0.60 ns
2.5 ns
2.5 ns
10
ns
8
ns
8
ns
8
ns
Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified
except V_OD, ΔV_OD and V_ID.
Note 6: All typicals are given for V_CC = +3.3V and T_A = +25°C, unless otherwise stated.
Note 7: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V.
Note 8: C_L includes probe and fixture capacitance.
Note 9: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, Z_O = 50Ω, t_r, t_f = <1.0 ns (0%–100%). To ensure fastest propagation delay and
minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge
rate, the better the AC performance.
Note 10: The DS92LV090AEP functions within datasheet specification when a resistive load is applied to the driver outputs.
Note 11: Propagation delays are guaranteed by design and characterization.
Note 12: t_SKD1 |t_PHLD–t_PLHD| is the worse case skew between any channel and any device over recommended operation conditions.
Note 13: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 14: V_OH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.
Note 15: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
Note 16: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge.
Note 17: "Testing and other quality control techniques are used to the extent deemed necessary to ensure product performance over the specified temperature
range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific
PARAMETRIC testing, product performance is assured by characterization and/or design."
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201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19