DS92LV090AEP Datasheet, PDF (2/14 Pages) Texas Instruments – DS92LV090AEP 9 Channel Bus LVDS Transceiver

DS92LV090AEP
OBSOLETE
June 15, 2009
9 Channel Bus LVDS Transceiver
General Description
The DS92LV090AEP is one in a series of Bus LVDS
transceivers designed specifically for the high speed, low
power proprietary backplane or cable interfaces. The device
operates from a single 3.3V power supply and includes nine
differential line drivers and nine receivers. To minimize bus
loading, the driver outputs and receiver inputs are internally
connected. The separate I/O of the logic side allows for loop
back support. The device also features a flow through pin out
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V com-
mon mode range and translates the differential Bus LVDS to
standard (TTL/CMOS) levels. (See Applications Information
Section for more details.)
ENHANCED PLASTIC
• Extended Temperature Performance of −40°C to +85°C
• Baseline Control - Single Fab & Assembly Site
• Process Change Notification (PCN)
• Qualification & Reliability Data
• Solder (PbSn) Lead Finish is standard
• Enhanced Diminishing Manufacturing Sources (DMS)
Support
Features
■ ^{Bus LVDS Signaling}
■ ^{3.2 nanosecond propagation delay max}
■ ^{Chip to Chip skew ±800ps}
■ ^{Low power CMOS design}
■ ^{High Signaling Rate Capability (above 100 Mbps)}
■ ^{0.1V to 2.3V Common Mode Range for V}_ID ^{= 200mV}
■ ^{±100 mV Receiver Sensitivity}
■ ^{Supports open and terminated failsafe on port pins}
■ ^{3.3V operation}
■ ^{Glitch free power up/down (Driver & Receiver disabled)}
■ ^{Light Bus Loading (5 pF typical) per Bus LVDS load}
■ ^{Designed for Double Termination Applications}
■ ^{Balanced Output Impedance}
■ ^{Product offered in 64 pin TQFP package}
■ ^{High impedance Bus pins on power off (V}_CC ^{= 0V)}
■ ^{Driver Channel to Channel skew (same device) 230ps}
typical
■ ^{Receiver Channel to Channel skew (same device) 370ps}
typical
Application
■ ^{Selected Military Applications}
■ ^{Selected Avionics Applications}
Ordering Infromation
PART NUMBER
DS92LV090ATVEP
(Notes 1, 2)
VID PART NUMBER
V62/04741-01
TBD
NS PACKAGE NUMBER (Note 3)
VEH64A
TBD
Note 1: For the following (Enhanced Plastic) version, check for availability: DS92LV090TVHXEP. Parts listed with an "X" are provided in Tape & Reel and
parts without an "X" are in Rails.
Note 2: FOR ADDITIONAL ORDERING AND PRODUCT INFORMATION, PLEASE VISIT THE ENHANCED PLASTIC WEB SITE AT: www.national.com/
mil
Note 3: Refer to package details under Physical Dimensions
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© 2009 National Semiconductor Corporation 201195
201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19
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