DS90LV032AQML Datasheet, PDF (8/14 Pages) Texas Instruments – DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

Applications Information
General application guidelines and hints for LVDS drivers and
receivers may be found in the following application notes:
www.national.com/lvds.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 10. This configuration provides a clean signaling
environment for the fast edge rates of the drivers . The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. A termination
resistor of 100Ω should be selected to match the media, and
is located as close to the receiver input pins as possible. The
termination resistor converts the driver output (current mode)
into a voltage that is detected by the receiver. Other configu-
rations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s),
and other impedance discontinuities as well as ground shift-
ing, noise margin limits, and total termination loading must be
taken into account.
The DS90LV032A differential line receiver is capable of de-
tecting signals as low as 100 mV, over a ±1V common-mode
range centered around +1.2V. This is related to the driver off-
set voltage which is typically +1.2V. The driven signal is
centered around this voltage and may shift ±1V around this
center point. The ±1V shifting may be the result of a ground
potential difference between the driver's ground reference
and the receiver's ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. Both
receiver input pins have a recommended operating input volt-
age range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection cir-
cuitry which will clamp the bus voltages.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. High fre-
quency ceramic (surface mount is recommended) 0.1μF in
parallel with 0.01μF, in parallel with 0.001μF at the power
supply pin as well as scattered capacitors over the printed
circuit board. Multiple vias should be used to connect the de-
coupling capacitors to the power planes A 10μF (35V) or
greater solid tantalum capacitor should be connected at the
power entry point on the printed circuit board.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a pow-
er/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential
impedance of your transmission medium (ie. cable) and ter-
mination resistor. Run the differential pair trace lines as close
together as possible as soon as they leave the IC (stubs
should be < 10mm long). This will help eliminate reflections
and ensure noise is coupled as common-mode. Lab experi-
ments show that differential signals which are 1mm apart
radiate far less noise than traces 3mm apart since magnetic
field cancellation is much better with the closer traces. Plus,
noise induced on the differential lines is much more likely to
appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference
between signals which destroys the magnetic field cancella-
tion benefits of differential signals and EMI will result. (Note
the velocity of propagation, v = c/Er where c (the speed of
light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on
the autoroute function for differential traces. Carefully review
dimensions to match differential impedance and provide iso-
lation for the differential lines. Minimize the number of vias
and other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use
arcs or 45° bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
TERMINATION
Use a resistor which best matches the differential impedance
of your transmission line. The resistor should be between
90Ω and 130Ω. Remember that the current mode outputs
need the termination resistor to generate the differential volt-
age. LVDS will not work without resistor termination. Typical-
ly, connect a single resistor across the pair at the receiver end.
Surface mount 1% to 2% resistors are best. PCB stubs, com-
ponent lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be <10mm
(12mm MAX)
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance
(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.
Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important
to remember:
Use controlled impedance media. The cables and connectors
you use should have a matched differential impedance of
about 100Ω. They should not introduce major impedance dis-
continuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation as common-mode (not differen-
tial mode) noise which is rejected by the receiver. For cable
distances < 0.5M, most cables can be made to work effec-
tively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3)
twisted pair cable works well, is readily available and relatively
inexpensive.
FAIL-SAFE FEATURE
The LVDS receiver is a high gain, high speed device that am-
plifies a small differential signal (20mV) to CMOS logic levels.
Due to the high gain and tight threshold of the receiver, care
should be taken to prevent noise from appearing as a valid
signal.
The receiver's internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection
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