DS90LV032AQML Datasheet, PDF (5/14 Pages) Texas Instruments – DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

Symbol
Parameter
t_PHZ
Disable Time High to Z
t_PZH
Enable Time Z to High
t_PZL
Enable Time Z to Low
Conditions
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = V_OH-0.5V,
R_L = 1kΩ.
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = 50%,
R_L = 1kΩ.
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = 50%,
R_L = 1kΩ.
Notes Min Max
Fig 3 & 4
12
Units
ns
Sub-
groups
9, 10, 11
Fig 3 & 4
20
ns
9, 10, 11
Fig 3 & 4
20
ns
9, 10, 11
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Derate @ 6.8mW/°C
Note 3: Human body model, 1.5 kΩ in series with 100 pF.
Note 4: Tested during V_OH/V_OL tests by applying appropriate voltage levels to the input pins of the device under test.
Note 5: Chip to chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
Note 6: The VCMR range is reduced for larger V_ID. Example: if V_ID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over
a common-mode range of 0V to 2.3V.
and Differential Pulse skew decrease
A V_ID
when
≤ ^{up to VCC − 0V may be applied to the RIN+/ RI− inputs with the Common-Mode voltage}
V_ID is increased from 200mV to 400mV. Skew specifications apply for 200mV V_ID
s_≤et8t0o0Vm_CVC/2o.vPerrothpeagcaotmiomn _odne-lay
mode range .
Note 7: Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any
event on the inputs.
Note 8: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
exceed maximum junction temperature.
Note 9: Tested during I_OZ tests by applying appropriate threshold voltage levels to the En and En* pins.
Note 10: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die
Parameter Measurement Information
20163903
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
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20163904
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
4