DS90LV031AQML_14 Datasheet, PDF (8/15 Pages) Texas Instruments – 3V LVDS Quad CMOS Differential Line Driver

DS90LV031AQML
SNLS204A – NOVEMBER 2011 – REVISED APRIL 2013
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The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output
to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or
power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω
termination resistor across the input pins. The unplugged cable can become a floating antenna which can
pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a
valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs
shorted and no external common-mode voltage applied.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.
Pin Descriptions
Pin No.
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
4
12
16
8
Figure 7. Driver Output Levels
Name
D_I
D_O+
D_O−
En
En*
V_CC
Gnd
Description
Driver input pin, TTL/CMOS compatible
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
Active high enable pin, OR-ed with En*
Active low enable pin, OR-ed with En
Power supply pin, +3.3V ± 0.3V
Ground pin
8
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