DS90LV031AQML_14 Datasheet, PDF (4/15 Pages) Texas Instruments – 3V LVDS Quad CMOS Differential Line Driver

DS90LV031AQML
SNLS204A – NOVEMBER 2011 – REVISED APRIL 2013
DS90LV031A Electrical Characteristics DC Parameters
The following conditions apply, unless otherwise specified.
DC: V_CC = 3.0/3.6V
Symbol
Parameter
Conditions
Notes
Min
Max
V_OD1
ΔV_OD1
V_OS
ΔV_OS
V_OH
V_OL
V_IH
V_IL
I_IH
I_IL
V_Cl
I_OS
I_Off
I_OZ
I_CC
I_CCL
I_CCZ
Differential Ouput Voltage
Δ in magnitude of V_OD1 for
complementary output States
R_L = 100Ω
R_L = 100Ω
Offset Voltage
R_L = 100Ω
Δ in Magnitude of V_OS for
R_L = 100Ω
Complementary Output States
Output Voltage High
Output Voltage Low
Input Voltage High
R_L = 100Ω
R_L = 100Ω
Input Voltage Low
Input Current
Input Current
Input Clamp Voltage
Output Short Circuit Current
Power-off Leakage
Output TRI-STATE Current
No Load Drivers Enabled
Supply Current
V_I = V_CC or 2.5V, V_CC = 3.6V
V_I = Gnd or 0.4V, V_CC = 3.6V
I_Cl = -8mA, V_CC = 3.0V
Enabled,
D_I = V_CC, D_O+ = 0V or
D_I = Gnd, D_O- = 0V
V_O = 0V or 3.6V
V_CC = 0V or V_CC = Open
En = 0.8V and En* = 2.0V
V_O = 0V or V_CC, V_CC = 3.6V
D_I = V_CC or Gnd
Loaded Drivers Enabled
Supply Current
Loaded or No Load Drivers
Disabled Supply Current
R_L = 100Ω All Channels,
D_I = V_CC or Gnd (all inputs)
D_I = V_CC or Gnd, En = Gnd,
En* = V_CC
(1) Tested during V_OH/V_OL tests.
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
(1)
(1)
250
1.125
0.9
2.0
Gnd
-9.0
450
50
1.625
50
1.85
V_CC
0.8
±10
±10
-1.5
±20
±10
18
35
12
DS90LV031A Electrical Characteristics AC Parameters
The following conditions apply, unless otherwise specified.
AC: V_CC = 3.0/3.3/3.6V, R_L = 100Ω, C_L = 20pF.
Symbol
Parameter
Conditions
Notes Min Max
t_PHLD
t_PLHD
t_SkD
t_Sk1
t_Sk2
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Skew t_PHLD - t_PLHD
Channel to Channel Skew
Chip to Chip Skew
Figure 4
and
Figure 5
Figure 4
and
Figure 5
(1)
(2)
0.3 3.5
0.3 3.5
1.5
1.75
3.2
Units
mV
mV
V
mV
V
V
V
V
µA
µA
V
mA
µA
µA
mA
mA
mA
Units
ns
ns
ns
ns
ns
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Sub-
groups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Sub-
groups
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
(1) Channel to Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with any event on the inputs.
(2) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
4
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