DS90LV001_14 Datasheet, PDF (8/22 Pages) Texas Instruments – 800 Mbps LVDS Buffer

DS90LV001
SNLS067E – JANUARY 2001 – REVISED APRIL 2013
APPLICATION INFORMATION
www.ti.com
MODE OF OPERATION
The DS90LV001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and
one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and
the unterminated receivers on the individual cards. Although it is generally recognized that this distance should
be as short as possible to maximize system performance, real-world packaging concerns and PCB designs often
make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the WSON
package, can improve system performance by allowing the receiver to be placed very close to the main
transmission line either on the backplane itself or very close to the connector on the card. Longer traces to the
LVDS receiver may be placed after the DS90LV001. This very small WSON package is a 75% space savings
over the SOIC package.
INPUT FAILSAFE
The receiver inputs of the DS90LV001 do not have internal failsafe biasing. For point-to-point and multidrop
applications with a single source, failsafe biasing may not be required. When the driver is off, the link is in-active.
If failsafe biasing is required, this can be accomplished with external high value resistors. Using the equations in
the LVDS Owner"s Manual Chapter 4, the IN+ should be pull to V_CC (3.3V) with 20kΩ and the IN− should be pull
to GND with 12kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a
minimum amount of distortion.
PCB LAYOUT AND POWER SYSTEM BYPASS
Circuit board layout and stack-up for the DS90LV001 should be designed to provide noise-free power to the
device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the
PCB power system which improves power supply filtering, especially at high frequencies, and makes the value
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum
capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the
power supply voltage being used. It is recommended practice to use two vias at each power pin of the
DS90LV001 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to
half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass
components.
8
Submit Documentation Feedback
Product Folder Links: DS90LV001
Copyright © 2001–2013, Texas Instruments Incorporated