DS90LV001_14 Datasheet, PDF (4/22 Pages) Texas Instruments – 800 Mbps LVDS Buffer

DS90LV001
SNLS067E – JANUARY 2001 – REVISED APRIL 2013
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾
Symbol
Parameter
Conditions
Min Typ Max Units
t_PHLD
t_PLHD
t_SKD1
t_SKD3
t_SKD4
t_LHT
t_HLT
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Pulse Skew |t_PLHD − t_PHLD|⁽²⁾⁽³⁾
Part to Part Skew⁽²⁾⁽⁴⁾
Part to Part Skew⁽²⁾⁽⁵⁾
Rise Time⁽²⁾
Fall Time⁽²⁾
R_L = 100Ω, C_L = 5pF
Figure 4 and Figure 5
R_L = 100Ω, C_L = 5pF
Figure 4 and Figure 6
1.0 1.4 2.0 ns
1.0 1.4 2.0 ns
20 200 ps
0
60
ps
400 ps
200 320 450 ps
200 310 450 ps
t_PHZ
Disable Time (Active High to Z)
t_PLZ
Disable Time (Active Low to Z)
R_L = 100Ω, C_L = 5pF
Figure 7 and Figure 8
3
25
ns
3
25
ns
t_PZH
Enable Time (Z to Active High)
25
45
ns
t_PZL
Enable Time (Z to Active Low)
t_DJ
LVDS Data Jitter, Deterministic (Peak-to-Peak)⁽⁶⁾ V_ID = 300mV; PRBS = 2²³ − 1 data; V_CM
= 1.2V at 800Mbps (NRZ)
25
45
ns
100 135 ps
t_RJ
LVDS Clock Jitter, Random⁽⁶⁾
V_ID = 300mV; V_CM = 1.2V at 400MHz
clock
2.2 3.5 ps
(1) All typical are given for V_CC = +3.3V and T_A = +25°C, unless otherwise stated.
(2) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT (process,
voltage and temperature) range.
(3) t_SKD1, |t_PLHD − t_PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4) t_SKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.
(5) t_SKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min|
differential propagation delay.
(6) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT range with
the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A
(digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a t_DJ = 21ps and t_RJ =
1.8ps.
4
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