DS90CF383_11 Datasheet, PDF (8/11 Pages) Texas Instruments – +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link—65 MHz

AC Timing Diagrams (Continued)
DS100033-18
FIGURE 11. Transmitter Power Down Delay
FIGURE 12. Transmitter LVDS Output Pulse Position Measurement
DS100033-26
DS90CF383 Pin Description — FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
I/O No.
I 28
O4
O4
I
1
O1
O1
I
1
I
4
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
7
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