DS15BR400_15 Datasheet, PDF (8/19 Pages) Texas Instruments – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

DS15BR400, DS15BR401
SNLS224G – AUGUST 2006 – REVISED APRIL 2013
APPLICATION INFORMATION
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INTERNAL TERMINATIONS
The DS15BR400 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω
resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the
device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to
minimize the output return loss and does not take the place of the 100 ohm termination at the inputs to the
receiving device. The integrated terminations improve signal integrity and decrease the external component
count resulting in space savings. The DS15BR401 has 100Ω output terminations only.
OUTPUT CHARACTERISTICS
The output characteristics of the DS15BRB400/DS15BR401 have been optimized for point-to-point backplane
and cable applications, and are not intended for multipoint or multidrop signaling.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all
input and output buffers and internal bias circuitry are powered off. When exiting powerdown mode, there is a
delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS
Output Switching Characteristics.
Upon asserting the power down function (PWDN = Low), and if the Pre-emphasis feature is enable, it is possible
for the driver output to source current for a short amount of time lifting the output common mode to V_DD. To
prevent this occurrence, a load discharge pull down path can be used on either output (1 kΩ to ground
recommended). Alternately, a commonly deployed external failsafe network will also provide this path (see
INPUT FAILSAFE BIASING). The occurrence of this is application dependant, and parameters that will effect if
this is of concern include: AC coupling, use of the powerdown feature, presence of the discharge path, presence
of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream LVDS
Receiver.
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. One pin is used to select the
pre-emphasis level for all outputs, off or on. The pre-emphasis boost is approximately 6 dB at 750 MHz.
Table 1. Pre-emphasis Control Selection Table
PEM
0
1
Pre-Emphasis
Off
On
INPUT FAILSAFE BIASING
Failsafe biasing of the LVDS link should be considered if the downstream Receiver is ON and enabled when the
source is in TRI-STATE, powered off, or removed. This will set a valid known input state to the active receiver.
This is accomplished by using a pull up resistor to V_DD on the ‘plus’ line, and a pull down resistor to GND on the
‘minus’ line. Resistor values are in the 750 Ohm to several kΩ range. The exact value depends upon the desired
common mode bias point, termination resistor(s) and desired input differential voltage setting. Please refer to
application note AN-1194 “Failsafe Biasing of LVDS interfaces” (SNLA051) for more information and a general
discussion.
DECOUPLING
Each power or ground lead of the DS15BR400 should be connected to the PCB through a low inductance path.
For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via
placement is immediately adjacent to the pin to avoid adding trace inductance. Placing power plane closer to the
top of the board reduces effective via length and its associated inductance.
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