DS15BR400_15 Datasheet, PDF (5/19 Pages) Texas Instruments – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

DS15BR400, DS15BR401
www.ti.com
SNLS224G – AUGUST 2006 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
LVDS INPUT DC SPECIFICATIONS (INn±)
V_TH
Differential Input High
Threshold ⁽²⁾
V_CM = 0.8V to 3.55V,
V_DD = 3.6V
V_TL
Differential Input Low
Threshold ⁽²⁾
V_CM = 0.8V to 3.55V,
V_DD = 3.6V
V_ID
Differential Input Voltage
V_CM = 0.8V to 3.55V, V_DD = 3.6V
V_CMR Common Mode Voltage Range V_ID = 150 mV, V_DD = 3.6V
C_IN2
LVDS Input Capacitance
IN+ or IN− to V_SS
I_IN
Input Current
V_IN = 3.6V, V_DD = 3.6V
V_IN = 0V, V_DD = 3.6V
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V_OD
Differential Output Voltage,
R_L = 100Ω external resistor between OUT+ and OUT−
0% Pre-emphasis ⁽²⁾
Figure 5
ΔV_OD
V_OS
ΔV_OS
Change in V_OD between
Complementary States
Offset Voltage ⁽³⁾
Change in V_OS between
Complementary States
C_OUT
I_OS
LVDS Output Capacitance
Output Short Circuit Current
OUT+ or OUT− to V_SS
OUT+ or OUT− Short to GND
OUT+ or OUT− Short to VDD
SUPPLY CURRENT (Static)
I_CC
Supply Current
All inputs and outputs enabled and active, terminated with
differential load of 100Ω between OUT+ and OUT-. PEM = L
I_CCZ
Supply Current - Power Down PWDN = L, PEM = L
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t_LHT
Differential Low to High
Transition Time ⁽⁴⁾
t_HLT
Differential High to Low
Transition Time ⁽⁴⁾
Use an alternating 1 and 0 pattern at 200 Mbps, measure
between 20% and 80% of V_OD.
Figure 6 , Figure 8
t_PLHD
t_PHLD
t_SKD1
t_SKCC
t_SKP
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Pulse Skew ⁽⁴⁾
Output Channel to Channel
Skew ⁽⁴⁾
Part to Part Skew ⁽⁴⁾
Use an alternating 1 and 0 pattern at 200 Mbps, measure at
50% V_OD between input to output.
Figure 6 , Figure 7
|t_PLHD–t_PHLD|
Difference in propagation delay (t_PLHD or t_PHLD) among all
output channels.
Common edge, parts at same temp and V_CC
Min
Typ
(1)
Max Units
0
100 mV
−100 0
mV
100
2400 mV
0.05
3.55 V
3.0
pF
−10
+10 µA
−10
+10 µA
250 360 500 mV
−35
35 mV
1.05 1.18 1.475 V
−35
35 mV
2.5
pF
−21 −40 mA
6
40 mA
175 215 mA
20 200 µA
170 250 ps
170 250 ps
1.0 2.0 ns
1.0 2.0 ns
10
60
ps
25
75
ps
550 ps
(2) Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
(3) Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
Copyright © 2006–2013, Texas Instruments Incorporated
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