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DS15BR400_15 Datasheet, PDF (6/19 Pages) Texas Instruments – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis
DS15BR400, DS15BR401
SNLS224G – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max Units
tJIT
Jitter (0% Pre-emphasis)
(5)
RJ - Alternating 1 and 0 at 750 MHz (6)
DJ - K28.5 Pattern, 1.5 Gbps (7)
TJ - PRBS 223-1 Pattern, 1.5 Gbps (8)
0.5 1.5 ps
14
30
ps
14
31
ps
tON
LVDS Output Enable Time
Time from PWDN to OUT± change from TRI-STATE to active.
Figure 9, Figure 10
20
µs
tOFF
LVDS Output Disable Time
Time from PWDN to OUT± change from active to TRI-STATE.
Figure 9, Figure 10
12
ns
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 50% duty cycle at 750 MHz, tr = tf = 50 ps
(20% to 80%).
(7) Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500 mV,
input common mode voltage = VICM = 1.2V, K28.5 pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50
ps (20% to 80%).
DC Test Circuits
1/4 DS15BR400
IN+
Power Supply
R
D
Power Supply
IN-
OUT+
OUT-
VOH
RL
VOL
Figure 5. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
Signal Generator
1/4 DS15BR400
IN+
OUT+
R
D
RL
IN-
OUT-
Figure 6. Differential Driver AC Test Circuit
Figure 7. Propagation Delay Timing Diagram
6
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