DRV8832-Q1 Datasheet, PDF (8/20 Pages) Texas Instruments – Low-Voltage Motor Driver IC

DRV8832-Q1
SLVSBW9C – APRIL 2013 – REVISED DECEMBER 2015
7.3 Feature Description
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7.3.1 PWM Motor Driver
The DRV8832-Q1 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry.
See Figure 7 for a block diagram of the motor control circuitry.
VCC
OCP
VCC
IN1
IN2
PWM
VSET
COMP
Pre-
drive
OCP
OUT 1
OUT2
DCM
/4
ITRIP
Integrator
DIFF
+
COMP
-
REF
ISENSE
Figure 7. Motor Control Circuitry
7.3.2 Bridge Control
The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic:
Table 1. H-Bridge Logic
IN1
IN2
0
0
0
1
1
0
1
1
OUT1
Z
L
H
H
OUT2
Z
H
L
H
Function
Sleep/coast
Reverse
Forward
Brake
When both bits are zero, the output drivers are disabled and the device is placed into a low-power sleep state.
The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep
mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to
the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, high-
speed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as
described in the following paragraph.
Because of the sleep mode functionality described previously, when applying an external PWM to the DRV8832-
Q1, hold one input logic high while applying a PWM signal to the other. If the logic input is held low instead, then
the device will cycle in and out of sleep mode, causing the FAULTn pin to pulse low on every sleep mode exit.
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