DRV8301_12 Datasheet, PDF (8/26 Pages) Texas Instruments – Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

DRV8301
SLOS719 – AUGUST 2011
ELECTRICAL CHARACTERISTICS (continued)
PVDD = 8-60 V, T_C = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
V_{GX_NORM}
I_oso1
I_osi1
I_oso2
I_osi2
I_oso3
I_osi3
R_{gate_off}
Gate driver Vgs voltage
Maximum source current setting 1, peak
Maximum sink current setting 1, peak
Source current setting 2, peak
Sink current setting 2, peak
Source current setting 3, peak
Sink current setting 3, peak
Gate output impedence during standby mode
when EN_GATE low (pins GH_x, GL_x)
PVDD = 8–60V
Vgs of FET equals to 2 V. REG 0x02
Vgs of FET equals to 8 V. REG 0x02
Vgs of FET equals to 2 V. REG 0x02
Vgs of FET equals to 8 V. REG 0x02
Vgs of FET equals to 2 V. REG 0x02
Vgs of FET equals to 8 V. REG 0x02
SUPPLY CURRENTS
I_{PVDD1_STB} PVDD1 supply current, standby
I_{PVDD1_OP} PVDD1 supply current, operating
EN_GATE is low. PVDD1 = 8V.
EN_GATE is high, no load on gate drive
output, switching at 10 kHz,
100 nC gate charge
I_{PVDD1_HIZ} PVDD1 Supply current, HiZ
INTERNAL REGULATOR VOLTAGE
EN_GATE is high, gate not switching
A_VDD
AVDD voltage
D_VDD
DVDD voltage
VOLTAGE PROTECTION
V_{PVDD_UV} Under voltage protection limit, PVDD
V_{GVDD_UV} Under voltage protection limit, GVDD
V_{GVDD_OV} Over voltage protection limit, GVDD
CURRENT PROTECTION, (VDS SENSING)
V_{DS_OC}
T_oc
T_{OC_PULSE}
Drain-source voltage protection limit
OC sensing response time
OCTW pin reporting pulse stretch length for OC
event
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MIN TYP MAX UNIT
9.5
11.5 V
1.7
A
2.3
A
0.7
A
1
A
0.25
A
0.5
A
1.6
2.4 kΩ
20 50 µA
15
mA
2 5 10 mA
6 6.5 7 V
3 3.3 3.6 V
6V
8V
16
V
0.125
2.4 V
1.5
µs
64
µs
8
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