DRV8301_12 Datasheet, PDF (10/26 Pages) Texas Instruments – Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

DRV8301
SLOS719 – AUGUST 2011
CURRENT SHUNT AMPLIFIER CHARACTERISTICS
T_C = 25°C unless otherwise specified
PARAMETER
TEST CONDITIONS
G1
Gain option 1
G2
Gain option 2
G3
Gain Option 3
G4
Gain Option 4
Tsettling Settling time to 1%
Tc = 0-60°C, G = 10, Vstep = 2 V
Tsettling Settling time to 1%
Tc = 0-60°C, G = 20, Vstep = 2 V
Tsettling Settling time to 1%
Tc = 0-60°C, G = 40, Vstep = 2 V
Tsettling Settling time to 1%
Tc = 0-60°C, G = 80, Vstep = 2 V
Vswing
Output swing linear range
Slew Rate
G = 10
DC_offset Offset error RTI
G = 10 with input shorted
Drift_offset Offset drift RTI
Ibias
Input bias current
Vin_com Common input mode range
Vin_dif
Differential input range
Vo_bias
Output bias
With zero input current, Vref up to 6 V
CMRR_OV
Overall CMRR with gain resistor
mismatch
CMRR at DC, gain = 10
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MIN
TYP
9.5
10
18
20
38
40
75
80
300
600
1.2
2.4
0.3
10
10
–0.15
–0.3
–0.5%
0.5×Vref
MAX
10.5
21
42
85
5.7
4
100
0.15
0.3
0.5%
UNIT
V/V
V/V
V/V
V/V
ns
µs
µs
µs
V
V/µs
mV
µV/C
µA
V
V
V
70
85
dB
BUCK CONVERTER CHARACTERISTICS
T_C = 25°C unless otherwise specified
PARAMETER
TEST CONDITIONS
V_UVLO
I_SD(PVDD2)
I_{NON_SW(PVDD2)}
Internal undervoltage lockout threshold
Shutdown supply current
Operating: nonswitching supply current
V_{EN_BUCK}
Enable threshold voltage
No voltage hysteresis, rising and falling
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V
VSENSE = 0.83 V, VIN = 12 V
No voltage hysteresis, rising and falling,
25°C
R_{DS_ON}
I_LIM
OTSD_BK
On-resistance
Current limit threshold
Thermal shutdown
VIN = 3.5 V, BOOT-PH = 3 V
VIN = 12 V, T_J = 25°C
F_sw
Switching frequency
RT = 200 kΩ
VSENSE falling
PWRGD
VSENSE threshold
VSENSE rising
VSENSE rising
VSENSE falling
Hysteresis
VSENSE falling
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V,
25°C
On resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
MIN TYP MAX UNIT
2.5
V
1.3
4 µA
116 136 µA
0.9 1.25 1.55 V
300
1.8 2.7
150
450 581
92%
94%
109%
107%
2%
mΩ
A
°C
720 kHz
10
nA
50
Ω
SPI CHARACTERISTICS (Slave Mode Only)
PARAMETER
TEST CONDITIONS
t_{SPI_READY}
SPI ready after EN_GATE transitions to
HIGH
PVDD > 8 V
t_CLK
t_CLKH
t_CLKL
Minimum SPI clock period
Clock high time
Clock low time
MIN TYP MAX UNIT
5
10 ms
100
ns
40
40
10
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