XIO2221 Datasheet, PDF (79/196 Pages) Texas Instruments – PCI Express™ TO 1394b OHCI WITH 1-PORT PHY

XIO2221
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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
4.60 GPIO Control Register
This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior
of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4
(SCL) and GPIO5 (SDA). See Table 4-34 for a complete description of the register contents.
PCI register offset:
Register type:
B4h
Read only, Read/Write
Default value:
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-34. GPIO Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:8
7 ⁽¹⁾
RSVD
GPIO7_DIR
R
Reserved. Return 00h when read.
RW
GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.
6⁽¹⁾ GPIO6_DIR
0 = Input (default)
1 = Output
RW
GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.
5⁽¹⁾ GPIO5_DIR
0 = Input (default)
1 = Output
RW
GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.
4⁽¹⁾ GPIO4_DIR
0 = Input (default)
1 = Output
RW
GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.
3⁽¹⁾ GPIO3_DIR
0 = Input (default)
1 = Output
RW
GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.
2⁽¹⁾ GPIO2_DIR
0 = Input (default)
1 = Output
RW
GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.
1⁽¹⁾ GPIO1_DIR
0 = Input (default)
1 = Output
RW
GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.
0⁽¹⁾ GPIO0_DIR
0 = Input (default)
1 = Output
RW
GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.
0 = Input (default)
1 = Output
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
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Classic PCI Configuration Space
79