XIO2221 Datasheet, PDF (68/196 Pages) Texas Instruments – PCI Express™ TO 1394b OHCI WITH 1-PORT PHY

XIO2221
SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
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4.42 MSI Message Data Register
This register contains the data that software programmed the bridge to send when it send a MSI message.
See Table 4-24 for a complete description of the register contents.
PCI register offset:
Register type:
6Ch
Read/Write
Default value:
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
FIELD NAME
15:4 MSG
3:0 MSG_NUM
Table 4-24. MSI Message Data Register Description
ACCESS
RW
RW
DESCRIPTION
System specific message. This field contains the portion of the message that the bridge
forwards unmodified.
Message number. This portion of the message field may be modified to contain the
message number is multiple messages are enable. The number of bits that are modifiable
depends on the number of messages enabled in the message control register.
1 message = No message data bits can be modified (default).
2 messages = Bit 0 can be modified.
4 messages = Bits 1:0 can be modified.
8 messages = Bits 2:0 can be modified.
16 messages = Bits 3:0 can be modified.
NOTE
Enabling MSI messaging in the XIO2221 has no effect.
4.43 SSID/SSVID Capability ID Register
This read-only register identifies the linked list item as the register for subsystem ID and subsystem
vendor ID capabilities. The register returns 0Dh when read.
PCI register offset:
Register type:
Default value:
80h
Read only
0Dh
BIT NUMBER
RESET STATE
76543210
00001101
4.44 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.
This register reads 90h pointing to the PCI Express capabilities registers.
PCI register offset:
Register type:
81h
Read only
Default value:
90h
BIT NUMBER
RESET STATE
76543210
10010000
68
Classic PCI Configuration Space
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