XIO2221 Datasheet, PDF (71/196 Pages) Texas Instruments – PCI Express™ TO 1394b OHCI WITH 1-PORT PHY

XIO2221
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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
4.50 Device Capabilities Register
This register indicates the device-specific capabilities of the bridge. See Table 4-26 for a complete
description of the register contents.
PCI register offset:
Register type:
94h
Read only
Default value:
0000 8002
BIT NUMBER
RESET STATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
BIT
31:28
27:26
FIELD NAME
RSVD
CSPLS
25:18 CSPLV
17:16 RSVD
15 RBER
14 PIP
13 AIP
12 ABP
11:9 EP_L1_LAT
8:6 EP_L0S_LAT
5
ETFS
4:3 PFS
2:0 MPSS
Table 4-26. Device Capabilities Register Description
ACCESS
R
RU
RU
R
R
R
R
R
RU
RU
R
R
R
DESCRIPTION
Reserved. Returns 0h when read.
Captured slot power limit scale. The value in this field is programmed by the host by issuing a
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8
are written to this field. The value in this field specifies the scale used for the slot power limit.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x1
Captured slot power limit value. The value in this field is programmed by the host by issuing a
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0
are written to this field. The value in this field in combination with the slot power limit scale value
(bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated
by multiplying the value in this field by the value in the slot power limit scale field.
Reserved. Return 000b when read.
Role-based error reporting. This bit is hardwired to 1 indicating that the XIO2221 supports
role-based error reporting.
Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not
implemented.
Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not
implemented.
Attention button present. This bit is hardwired to 0b indicating that an attention button is not
implemented.
Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a
transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY
field (bits 15:13) in the general control register (offset D4h, see Section 4.66). The default value
for this field is 000b, which indicates a range less than 1s. This field cannot be programmed to
be less than the latency for the PHY to exit the L1 state.
Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a
transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY
field (bits 18:16) in the general control register (offset D4h, see Section 4.66). The default value
for this field is 000b, which indicates a range less than 1s. This field cannot be programmed to
be less than the latency for the PHY to exit the L0s state.
Extended tag field supported. This field indicates the size of the tag field not supported.
Phantom functions supported. This field is read-only 00b indicating that function numbers are
not used for phantom functions.
Maximum payload size supported. This field indicates the maximum payload size that the
device can support for TLPs. This field is encoded as 010b indicating the maximum payload
size for a TLP is 512 bytes.
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Classic PCI Configuration Space
71