COP8SBR9_15 Datasheet, PDF (78/104 Pages) Texas Instruments – 8-Bit CMOS Flash Based Microcontroller with 32k Memory

COP8SBR9, COP8SCR9, COP8SDR9
SNOS537I – JUNE 2000 – REVISED MARCH 2013
1/t_C > 5 kHz—No clock rejection.
1/t_C < 10 Hz—Ensured clock rejection.
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Key
Data
Match
Don't Care
Mismatch
Don't Care
Table 5-21. WATCHDOG Service Actions
Window
Data
Match
Mismatch
Don't Care
Don't Care
Clock
Monitor
Match
Don't Care
Don't Care
Mismatch
Action
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
5.15.3 WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET.
• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG
having the maximum service window selected.
• The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed
once, during the initial WATCHDOG service following RESET.
• The initial WATCHDOG service must match the key data value in the WATCHDOG Service register
WDSVR in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid
WATCHDOG errors.
• The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any
attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0's.
• The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes.
• The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently,
the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error
(provided that the CLOCK MONITOR enable option has been selected by the program). Likewise, a
device with WATCHDOG enabled in the Option but with the WATCHDOG output not connected to
RESET, will draw excessive HALT current if placed in the HALT mode. The clock Monitor will pull the
WATCHDOG output low and sink current through the on-chip pull-up resistor.
• The WATCHDOG service window will be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced for at least 2048 Idle Timer clocks following
HALT, but must be serviced within the selected window to avoid a WATCHDOG error.
• The IDLE timer T0 is not initialized with external RESET.
• The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the
T0PND flag. The T0PND flag is set whenever the selected bit of the IDLE counter toggles (every 4, 8,
16, 32 or 64k Idle Timer clocks). The user is responsible for resetting the T0PND flag.
• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the
WATCHDOG should not be serviced for at least 2048 Idle Timer clocks following IDLE, but must be
serviced within the selected window to avoid a WATCHDOG error.
• Following RESET, the initial WATCHDOG service (where the service window and the CLOCK
MONITOR enable/disable must be selected) may be programmed anywhere within the maximum
service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG
service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG
error.
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Functional Description
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