COP8SBR9_15 Datasheet, PDF (51/104 Pages) Texas Instruments – 8-Bit CMOS Flash Based Microcontroller with 32k Memory

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COP8SBR9, COP8SCR9, COP8SDR9
SNOS537I – JUNE 2000 – REVISED MARCH 2013
NOTE
To ensure accurate operation upon start-up of the device using Multi-Input Wake-up, the
instruction in the application program used for entering the HALT mode should be followed
by two consecutive NOP (no-operation) instructions.
5.12.3.1.5 Options
This device has two options associated with the HALT mode. The first option enables the HALT mode
feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option
will cause the microcontroller to ignore any attempts to HALT the device under software control. Note that
this device can still be placed in the HALT mode by stopping the clock input to the microcontroller, if the
program memory is masked ROM. See the Option section for more details on this option bit.
Figure 5-14. Wake-up from HALT
5.12.3.2 High Speed Idle Mode
In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with
the HALT mode. However, the high speed oscillator, IDLE Timer (Timer T0), and Clock Monitor continue
to operate, allowing real time to be maintained. The device remains idle for a selected amount of time up
to 65,536 instruction cycles, or 32.768 milliseconds with a 2 MHz instruction clock frequency, and then
automatically exits the IDLE mode and returns to normal program execution.
The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G
data register).
The IDLE Timer window is selectable from one of five values, 4k, 8k, 16k, 32k or 64k instruction cycles.
Selection of this value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state.
The IDLE Timer runs continuously at the instruction clock rate, whether or not the device is in the IDLE
mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an
interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer
interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However,
the instruction which was started as the part entered the IDLE mode is completed before the interrupt is
serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must
reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode.
As with the HALT mode, this device can also be returned to normal operation with a reset, or with a Multi-
Input Wake-up input. Upon reset the ITMR register is cleared and the ITMR register selects the 4,096
instruction cycle tap of the Idle Timer.
Copyright © 2000–2013, Texas Instruments Incorporated
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Functional Description
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