COP8SBR9_15 Datasheet, PDF (26/104 Pages) Texas Instruments – 8-Bit CMOS Flash Based Microcontroller with 32k Memory

COP8SBR9, COP8SCR9, COP8SDR9
SNOS537I – JUNE 2000 – REVISED MARCH 2013
www.ti.com
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
T2CNTRL: CLEARED
T3CNTRL: CLEARED
HSTCR: CLEARED
ITMR: Cleared except Bit 6 (HSON) = 1
Accumulator, Timer 1, Timer 2 and Timer 3:
RANDOM after RESET
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
Initialized to RAM address 06F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
S Register: CLEARED
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
USART:
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
ISP CONTROL:
ISPADLO: CLEARED
ISPADHI: CLEARED
PGMTIM: PRESET TO VALUE FOR 10 MHz CKI
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG logic and the Clock Monitor
detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set.
The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG
service window bits being initialized high default to the maximum WATCHDOG service
window of 64k T0 clock cycles. The Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached the minimum specified frequency at
the termination of reset. A Clock Monitor error will cause an active low error output on pin
G1. This error output will continue until 16–32 T0 clock cycles following the clock frequency
reaching the minimum specified value, at which time the G1 output will go high.
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Functional Description
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Product Folder Links: COP8SBR9 COP8SCR9 COP8SDR9