TM4C1290NCPDT Datasheet, PDF (771/1628 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1290NCPDT Microcontroller
Register 27: GPIO Wake Pin Enable (GPIOWAKEPEN), offset 0x540
This register is used to configure K[7:4] as a wake enable source for the hibernation module. The
wake level must be programmed in the GPIOWAKELVL register at offset 0x544. In order for this
register configuration to become implemented, the WUUNLK bit needs to be set in the HIBIO register
at offset 0x02C in the hibernation module.
Note: This register is only available on Port K.
GPIO Wake Pin Enable (GPIOWAKEPEN)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
Offset 0x540
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WAKEP7 WAKEP6 WAKEP5 WAKEP4
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
Name
reserved
WAKEP7
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0
K[7] Wake Enable
Value Description
0 Wake-on level is not enabled.
1 Wake-on level is enabled.
6
WAKEP6
RW
0
K[6] Wake Enable
Value Description
0 Wake-on level is not enabled.
1 Wake-on level is enabled.
June 18, 2014
771
Texas Instruments-Production Data