TM4C1237E6PM Datasheet, PDF (714/1277 Pages) Texas Instruments – Tiva Microcontroller

General-Purpose Timers
Bit/Field
13
12
11:10
9
8
Name
TBOTE
reserved
TBEVENT
TBSTALL
TBEN
Type
RW
RO
RW
RW
RW
Reset
0
0
0x0
0
0
Description
GPTM Timer B Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output Timer B ADC trigger is disabled.
1 The output Timer B ADC trigger is enabled.
Note:
The timer must be configured for one-shot or periodic
time-out mode to produce an ADC trigger assertion.
The GPTM does not generate triggers for match,
compare events or compare match events.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 809).
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
Note:
If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 Timer B continues counting while the processor is halted by the
debugger.
1 Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
GPTM Timer B Enable
The TBEN values are defined as follows:
Value Description
0 Timer B is disabled.
1 Timer B is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
714
June 12, 2014
Texas Instruments-Production Data