TM4C1237E6PM Datasheet, PDF (24/1277 Pages) Texas Instruments – Tiva Microcontroller

Table of Contents
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 486
Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 487
Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 491
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 493
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 495
Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 497
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 498
Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ............................................... 499
Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................ 500
Internal Memory ........................................................................................................................... 501
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 519
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 520
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 521
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 523
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 526
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 528
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 531
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 532
Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 533
Register 10: Flash Size (FSIZE), offset 0xFC0 .................................................................................... 534
Register 11: SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 535
Register 12: ROM Software Map (ROMSWMAP), offset 0xFCC ........................................................... 536
Register 13: EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 537
Register 14: EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 538
Register 15: EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 539
Register 16: EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 540
Register 17: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 541
Register 18: EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 542
Register 19: EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 544
Register 20: EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 546
Register 21: EEPROM Protection (EEPROT), offset 0x030 ................................................................. 547
Register 22: EEPROM Password (EEPASS0), offset 0x034 ................................................................. 549
Register 23: EEPROM Password (EEPASS1), offset 0x038 ................................................................. 549
Register 24: EEPROM Password (EEPASS2), offset 0x03C ................................................................ 549
Register 25: EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 550
Register 26: EEPROM Block Hide (EEHIDE), offset 0x050 .................................................................. 551
Register 27: EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 552
Register 28: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 553
Register 29: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 554
Register 30: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 555
Register 31: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 555
Register 32: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 556
Register 33: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 556
Register 34: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 557
Register 35: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 560
Register 36: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 560
Register 37: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 560
Register 38: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 560
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June 12, 2014
Texas Instruments-Production Data