TM4C1237E6PM Datasheet, PDF (125/1277 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237E6PM Microcontroller
3.1.4.3
3.1.5
Table 3-5. AP Bit Field Encoding (continued)
AP Bit Field
110
111
Privileged
Permissions
RO
RO
Unprivileged
Permissions
RO
RO
Description
Read-only, by privileged or unprivileged software.
Read-only, by privileged or unprivileged software.
MPU Configuration for a Tiva™ C Series Microcontroller
Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU
should be programmed as shown in Table 3-6 on page 125.
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers
Memory Region
Flash memory
Internal SRAM
External SRAM
Peripherals
TEX
000b
000b
000b
000b
S
C
B
Memory Type and Attributes
0
1
0
Normal memory, non-shareable, write-through
1
1
0
Normal memory, shareable, write-through
1
1
1
Normal memory, shareable, write-back,
write-allocate
1
0
1
Device memory, shareable
In current Tiva™ C Series microcontroller implementations, the shareability and cache policy
attributes do not affect the system behavior. However, using these settings for the MPU regions
can make the application code more portable. The values given are for typical situations.
MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 87 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 172 for more information.
Floating-Point Unit (FPU)
This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides:
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point and
floating-point data formats, and floating-point constant instructions. The FPU provides floating-point
computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for
Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision
extension registers can also be accessed as 16 doubleword registers for load, store, and move
operations.
June 12, 2014
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