LM3S5762_14 Datasheet, PDF (713/851 Pages) Texas Instruments – Microcontroller

Stellaris^® LM3S5762 Microcontroller
OTG A /
Host
OTG B /
Device
31
Type RO
Reset
0
15
Type RO
Reset
0
Register 89: USB External Power Control (USBEPC), offset 0x400
This 32-bit register specifies the function of the two-pin external power interface (USB0EPEN and
USB0PFLT). The assertion of the power fault input may generate an automatic action, as controlled
by the hardware configuration registers. The automatic action is necessary because the fault condition
may require a response faster than one provided by firmware.
USB External Power Control (USBEPC)
Base 0x4005.0000
Offset 0x400
Type R/W, reset 0x0000.0000
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PFLTACT
reserved PFLTAEN PFLTSEN PFLTEN reserved EPENDE
EPEN
RO
RO
RO
RO
RO
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:10
9:8
Name
reserved
PFLTACT
Type
RO
R/W
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
Power Fault Action
This bit field specifies how the USB0EPEN signal is changed when
detecting a USB power fault.
Value Description
0x0 Unchanged
USB0EPEN is controlled by the combination of the EPEN and
EPENDE bits.
0x1 Tristate
USB0EPEN is undriven (tristate).
0x2 Low
USB0EPEN is driven Low.
0x3 High
USB0EPEN is driven High.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 17, 2014
713
Texas Instruments-Production Data