LM3S5R36 Datasheet, PDF (712/1062 Pages) Texas Instruments – Stellaris® LM3S5R36 Microcontroller

Inter-Integrated Circuit (I²C) Interface
15.3.3.2
I²C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by setting the DATAIM bit in the I²C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I²C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I²C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the
I²C Slave Interrupt Clear (I2CSICR) register.
In addition, the slave module can generate an interrupt when a start and stop condition is detected.
These interrupts are enabled by setting the STARTIM and STOPIM bits of the I²C Slave Interrupt
Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I²C
Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I²C Slave Raw Interrupt Status (I2CSRIS) register.
15.3.4
Loopback Operation
The I²C modules can be placed into an internal loopback mode for diagnostic or debug work by
setting the LPBK bit in the I²C Master Configuration (I2CMCR) register. In loopback mode, the
SDA and SCL signals from the master and slave modules are tied together.
15.3.5
Command Sequence Flow Charts
This section details the steps required to perform the various I²C transfer types in both master and
slave mode.
15.3.5.1 I²C Master Command Sequences
The figures that follow show the command sequences available for the I²C master.
712
January 21, 2012
Texas Instruments-Production Data