LM3S5R36 Datasheet, PDF (71/1062 Pages) Texas Instruments – Stellaris® LM3S5R36 Microcontroller

Stellaris^® LM3S5R36 Microcontroller
Table 2-2. Processor Register Map
Offset Name
Type
-
R0
R/W
-
R1
R/W
-
R2
R/W
-
R3
R/W
-
R4
R/W
-
R5
R/W
-
R6
R/W
-
R7
R/W
-
R8
R/W
-
R9
R/W
-
R10
R/W
-
R11
R/W
-
R12
R/W
-
SP
R/W
-
LR
R/W
-
PC
R/W
-
PSR
R/W
-
PRIMASK
R/W
-
FAULTMASK
R/W
-
BASEPRI
R/W
-
CONTROL
R/W
Reset
Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0xFFFF.FFFF
-
0x0100.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Cortex General-Purpose Register 0
Cortex General-Purpose Register 1
Cortex General-Purpose Register 2
Cortex General-Purpose Register 3
Cortex General-Purpose Register 4
Cortex General-Purpose Register 5
Cortex General-Purpose Register 6
Cortex General-Purpose Register 7
Cortex General-Purpose Register 8
Cortex General-Purpose Register 9
Cortex General-Purpose Register 10
Cortex General-Purpose Register 11
Cortex General-Purpose Register 12
Stack Pointer
Link Register
Program Counter
Program Status Register
Priority Mask Register
Fault Mask Register
Base Priority Mask Register
Control Register
See
page
72
72
72
72
72
72
72
72
72
72
72
72
72
73
74
75
76
80
81
82
83
2.3.4
Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 70.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
January 21, 2012
71
Texas Instruments-Production Data