AM1705DPTPA3 Datasheet, PDF (71/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
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5.12.4 EMIFB Electrical Data/Timing
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
No.
19 t_su(DV-CLKH)
20 t_h(CLKH-DIV)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
t_c(CLK)
t_w(CLK)
t_d(CLKH-CSV)
t_{oh(CLKH-CSIV)}
t_d(CLKH-DQMV)
t_{oh(CLKH-DQMIV)}
t_d(CLKH-AV)
t_oh(CLKH-AIV)
t_d(CLKH-DV)
t_oh(CLKH-DIV)
t_d(CLKH-RASV)
t_{oh(CLKH-RASIV)}
t_d(CLKH-CASV)
t_{oh(CLKH-CASIV)}
t_d(CLKH-WEV)
t_{oh(CLKH-WEIV)}
t_{dis(CLKH-DHZ)}
t_{ena(CLKH-DLZ)}
Table 5-24. EMIFB SDRAM Interface Timing Requirements
PARAMETER
MIN
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK rising
0.8
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK rising
1.5
Table 5-25. EMIFB SDRAM Interface Switching Characteristics
PARAMETER
Cycle time, EMIF clock EMB_CLK
Pulse width, EMIF clock EMB_CLK high or low
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] valid
Output hold time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] invalid
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] 3-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
MIN
6.579
2.63
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
MAX
UNIT
ns
ns
MAX
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications
71
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