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AM1705DPTPA3 Datasheet, PDF (7/164 Pages) Texas Instruments – AM1705 ARM Microprocessor | |||
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AM1705
www.ti.com
SPRS657D â FEBRUARY 2010 â REVISED MARCH 2013
Revision History (continued)
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 5.5
Reset
Section 5.5.1, Power-On Reset (POR):
⢠Updated/Changed "RTCK is maintained active through a POR." to "RTCK/GP7[14] is maintained active
through a POR."
Section 5.5.2, Warm Reset:
⢠Updated/Changed âA warm reset provides â¦â paragraph
⢠Updated/Changed "RTCK is maintained active through a warm reset." to "RTCK/GP7[14] is maintained
active through a warm reset."
Section 5.8.1.4
AINTC System
Interrupt
Assignments on the
device
Table 5-7, AINTC System Interrupt Assignments:
⢠Updated/Changed SYSTEM INTERRUPT 27 INTERRUPT NAME from âPROTERRâ to
âMPU_BOOTCFG_ERRâ
⢠Updated/Changed SYSTEM INTERRUPT 27 SOURCE from âSYSCFG Protection Shared Interruptâ to
âShared MPU and SYSCFG Address/Protection Error Interrupt"
Section 5.8.1.5
Table 5-8, AINTC Memory Map:
AINTC Memory Map ⢠Deleted "[0]" to 0xFFFE F500 "HIER" REGISTER NAME
Section 5.11
Section 5.11.2, EMIFA Connection Examples:
External Memory
Interface A (EMIFA) ⢠Added new Subsection
Section 5.12
Figure 5-17, EMIFB Functional Block Diagram:
External Memory
Interface B (EMIFB) ⢠Added MPU2 block to figure
Section 5.12.1, EMIFB SDRAM Loading Limitations:
⢠Moved subsection from Interfacing to SDRAM section to under Section 5.12.1, External Memory
Interface B (EMIFB)
⢠Updated/Changed âEMIFB supports SDRAM up to 133 MHz â¦â to âEMIFB supports SDRAM up to 152
MHz â¦â
Section 5.12.2
Interfacing to
SDRAM
Section 5.12.2, EMIFB Supported SDRAM Configurations:
⢠Updated/Changed the table to include 8-bit SDRAM Memory Data Bus Width entries
⢠Updated/Changed "Number of Memories" column from "2" to "1" for the 16-Bit data bus width
Section 5.12.4
EMIFB Electrical
Data/Timing
Table 5-25, EMIFB SDRAM Interface Switching Characteristics:
⢠Updated/Changed PARAMETER No. 1, tc(CLK) Cycle time, EMIF clock EMB_CLK MIN value from â7.5â
to â6.579â ns
⢠Updated/Changed PARAMETER No. 2, tw(CLK) Pulse width, EMIF clock EMB_CLK high or low MIN
value from â3â to â2.63â ns
Section 5.26.1
Power Domain and
Module Topology
Section 5.26.1.1, Power Domain States:
⢠Added new subsection
Section 5.29
Section 5.29.1, JTAG Peripheral Register Description(s) â JTAG ID Register (DEVIDR0):
IEEE 1149.1 JTAG ⢠Added Silicon Revisions "3.0" and "2.1" to the "0x9B7D F02F for silicon revision 2.0" bullet
Section 6.1.2
Device and
Development-
Support Tool
Nomenclature
Updated/Changed subsection title from âDevice Nomenclatureâ to âDevice and Development-Support Tool
Nomenclature"
Figure 6-1, Device Nomenclature:
⢠Updated/Changed Silicon Revision to include Revision 3.0
Section 7
Mechanical
Packaging and
Orderable
Information
⢠Deleted âMechanical Drawingsâ section
⢠Deleted Packaging Materials Information subsection (was Section 7.1 in the previous revision), duplicate
information
⢠Added Section 7.3, Packaging Information
Copyright © 2010â2013, Texas Instruments Incorporated
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