TLC5618ACDR Datasheet, PDF (7/24 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156G – JULY 1997 – REVISED APRIL 2001
operating characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref(REFIN) = 2.048 V (unless otherwise noted) (continued)
digital input timing requirements
tsu(DS)
Setup time, DIN before SCLK low
th(DH)
Hold time, DIN valid after SCLK low
tsu(CSS) Setup time, CS low to SCLK low
tsu(CS1) Setup time, SCLK ↑ to CS ↑, external end-of-write
tsu(CS2) Setup time, SCLK ↑ to CS ↓, start of next write cycle
tw(CL)
Pulse duration, SCLK low
tw(CH)
Pulse duration, SCLK high
† _{Not production tested for Q and M suffixes.}
C and I suffixes
Q and M suffixes
MIN NOM MAX UNIT
5
ns
8
5
ns
5
ns
10
ns
5^†
ns
25
ns
25
ns
CS
tsu(CSS)
tw(CL)
tw(CH)
tsu(CS1)
tsu(CS2)
SCLK
(see Note A)
tsu(DS)
ÎÎÎÎÎÎ _DIN
D15
DAC A/B
OUT
th(DH)
D14
D13
ÏÏÏÏÏÏÏÏÏÏÏÏ _{Program Bits (4)}
ÎÎÎÎÎÎÎ _D12
D11 D0
ÏÏÏÏÏÎÎÎÎÎÏÎÏÎ DAC Data
ÏÏÏÏÏ ÏÏ ^{Bits (12)}
ts
NOTE A: SCLK must go high after the 16th falling clock edge.
≤ Final Value ±0.5 LSB
Figure 1. Timing Diagram for the TLC5618A
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