TLC5618ACDR Datasheet, PDF (13/24 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
APPLICATION INFORMATION
SLAS156G – JULY 1997 – REVISED APRIL 2001
Table 1. Binary Code Table (0 V to 2 V_REFIN Output)_, Gain = 2
1111
1000
1000
0111
0000
INPUT
1111
:
0000
0000
1111
:
0000
1111
0001
0000
1111
0001
ǒ Ǔ^OUTPUT
2
VREFIN
4095
4096
:
ǒ Ǔ ₂
VREFIN
2049
4096
ǒ Ǔ _{+ 2}
VREFIN
2048
4096
VREFIN
ǒ Ǔ ₂
VREFIN
2047
4096
ǒ Ǔ^:
2
VREFIN
1
4096
0000
0000
0000
0V
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 µs or 2.5 µs, typical to within ± 0.5 LSB of final value.
external reference
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5618 timing. The maximum serial clock rate is:
+ _{ǒ Ǔ ) ǒ Ǔ} + f(SCLK)max
1
tw _{CH min} tw _{CL min}
20 MHz
+ ǒ _{ǒ Ǔ} ) _{ǒ Ǔ}Ǔ ) _{ǒ Ǔ} ^{The digital update rate is limited by the chip-select period, which is:}
tp(CS) 16 tw _CH tw _CL
tsu _CS1
This equals an 810-ns or 1.23-MHz update rate. However, the DAC settling time to 12 bits limits the update rate
for full-scale input step transitions.
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