TLC5618ACDR Datasheet, PDF (5/24 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156G – JULY 1997 – REVISED APRIL 2001
electrical characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref(REFIN) = 2.048 V (unless otherwise noted)
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Resolution
12
bits
EZS
EG
PSRR
Integral nonlinearity (INL), end point adjusted
Differential nonlinearity (DNL)
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
Gain error
Gain error temperature coefficient
Zero scale
Power-supply rejection ratio
Gain
Zero scale
Gain
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 5
Vref(REFIN) = 2.048 V,
See Notes 7 and 8
See Note 1
See Note 2
See Note 3
See Note 4
C and I suffixes
Q and M suffixes
See Note 6
Slow
Fast
± 0.5
3
1
65
65
65
65
±4
±1
± 12
± 0.29
± 0.60
LSB
LSB
mV
ppm/°C
% of FS
voltage
ppm/°C
dB
NOTES:
1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
OUT A and OUT B output specifications
PARAMETER
VO
Voltage output range
Output load regulation accuracy
IOSC(sink)
Output short circuit sink current
TEST CONDITIONS
RL = 10 kΩ
VO(OUT) = 4.096 V, RL = 2 kΩ
VO(A _OUT) = VDD,
VO(B _OUT) = VDD,
Input code zero
Fast
Slow
MIN TYP MAX
UNIT
0
VDD–0.4
V
± 0.29
% of FS
voltage
38
mA
23
IOSC(source) Output short circuit source current
VO(A _OUT) = 0 V,
VO(B _OUT) = 0 V,
Full-scale code
Fast
Slow
–54
mA
–29
IO(sink)
IO(source)
Output sink current
Output source current
VO(OUT) = 0.25 V
VO(OUT) = 4.2 V
5
mA
5
mA
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