THS1230_15 Datasheet, PDF (7/23 Pages) Texas Instruments – 3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL

THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating conditions (AV_DD = DV_DD = 3.3 V, f_s = 30 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, T_min to T_max) (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP MAX UNIT
DC ACCURACY (LINEARITY)
Number of missing codes
All modes
0 codes
DNL Differential nonlinearity
All modes
±0.4
±1 LSB
INL
Integral nonlinearity
All modes
–2.5 ±1.2
2 LSB
Offset error
All modes
0.7 1.2 %FSR
Gain error
All modes
1.1 3.5 %FSR
DYNAMIC PERFORMANCE⁽¹⁾
ENOB Effective number of bits
THD Total harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise + distortion
SFDR Spurious free dynamic range
Analog input bandwidth
f_i = 3.58 MHz
f_i = 10 MHz
f_i = 15 MHz
f_i = 3.58 MHz
f_i = 10 MHz
f_i = 15 MHz
f_i = 3.58 MHz
f_i = 10 MHz
f_i = 15 MHz
f_i = 3.58 MHz
f_i = 10 MHz
f_i = 15 MHz
f_i = 3.58 MHz
f_i = 10 MHz
f_i = 15 MHz
10.9
10.4 10.6
10.4
–76
–74
–72.5
68
64.5 65.6
64.6
67.4
64
65
64.5
78.1
67
74
72
180
Bits
–65 dB
dB
dB
dB
MHz
Differential phase, DP
0.12
degree
G_(diff) Differential gain
TIMING (all supplies = 3.3 V)
0.01%
f_CLK
Clock frequency⁽²⁾
Clock duty cycle
5
45%
50%
30
55%
MHz
t_d(O)
t_d(PZ)
t_d(EN)
Output delay time
Delay time, output disable to Hi-Z output
Delay time, output enable to output valid
Latency
7
19 ns
3.2
ns
5
19 ns
5 cycles
(1) Input amplitudes for all single tone dynamic tests are at –1 dBFS, all supplies = 3.3 V.
(2) The clock frequency may be extended to 5 MHz without degradation in specified performance.
7