THS1230_15 Datasheet, PDF (16/23 Pages) Texas Instruments – 3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL

THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
www.ti.com
When clocking output data from THS1230, it is important to observe its timing relation to CLK. The pipeline ADC
delay is 5 clock cycles to which the maximum output propagation delay needs to be added.
THS1230
DA11
DA0 ₁₂
SN74ALVCH16841
1D9
1Q9
1D0
1Q0
12
2D1
2Q1
2D0
2Q0
ASIC
or
DSP
2D7
2Q9
2D2
2Q2
LE
OE
Figure 20. Buffered Output Connection
THS1230
DA11
DA0 ₁₂
CLK
FIFO
D11
1Q15
D0
1Q0 ₁₆
D15
D12 _{HF flag}
WRTCLK
DSP
INTR
30 MHz
Clock
Figure 21. FIFO Connection
Layout, Decoupling and Grounding Rules
Proper grounding and layout of the PCB on which THS1230 is populated is essential to achieve the stated
performance. It is advised to use separate analog and digital ground planes that are spliced underneath the IC.
THS1230 has digital and analog pins on opposite sides of the package to make this easier. Because there is no
connection internally between analog and digital grounds, they have to be joined on the PCB. It is advised to do
this at one point in close proximity to THS1230.
Because of the high sampling rate and switched-capacitor architecture, THS1230 generates transients on the
supply and reference lines. Proper decoupling of these lines is therefore essential. Decoupling is recommended
as shown in the schematic of the THS1230 evaluation module in Figure 22.
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