LMX2571 Datasheet, PDF (7/61 Pages) Texas Instruments – Low-Power, High-Performance PLLatinum RF Synthesizer

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LMX2571
SNAS654 – MARCH 2015
6.6 Timing Requirements
3.15 V ≤ V_CC ≤ 3.45 V, V_IO = V_CC, –40 °C ≤ T_A ≤ 85 °C, except as specified. Typical values are at V_CC = V_IO = 3.3 V, T_A = 25
°C.
MIN NOM MAX UNIT
MICROWIRE TIMING
t_ES
t_CS
t_CH
t_CWH
t_CWL
t_CES
t_EWH
Clock to enable low time
Data to clock setup time
Data to clock hold time
Clock pulse width high
Clock pulse width low
Enable to clock setup time
Enable pulse width high
See Figure 1
5
ns
2
ns
2
ns
5
ns
5
ns
5
ns
2
ns
DATA
MSB
LSB
tCS tCH
CLK
tCWL tCWH
tES
tCES
LE
tEWH
Figure 1. MICROWIRE Timing Diagram
There are several other considerations for programming:
• A slew rate of at least 30 V/µs is recommended for the CLK, DATA and LE. The same apply for other digital
control signals such as FSK_D[0:2] and FSK_DV signals.
• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE
signal, the data is sent from the shift register to an active register.
• The LE pin may be held high after programming, causing the LMX2571 to ignore clock pulses.
• When CLK or DATA lines are shared between devices, it is recommended to divide down the voltage to the
CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.
• If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines
are shared with other parts, the phase noise may be degraded during the time of this programming.
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