LMX2571 Datasheet, PDF (49/61 Pages) Texas Instruments – Low-Power, High-Performance PLLatinum RF Synthesizer

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LMX2571
SNAS654 – MARCH 2015
To enable external VCO operation, set the following bits:
Table 43. PLL Duplex Mode Register Settings Summary
CONFIGURATION PARAMETER
Charge pump polarity
External VCO charge pump gain
Base charge pump current
Select PLL mode operation
CHDIV3 divider
REGISTER BITS
EXTVCO_CP_POL
EXTVCO_CP_GAIN
EXTVCO_CP_IUP
EXTVCO_CP_IDN
EXTVCO_SEL_F1, EXTVCO_SEL_F2
EXTVCO_CHDIV_F1, EXTVCO_CHDIV_F2
SETTING
0 = Positive
1 = 1x
8 = 1250 µA
8 = 1250 µA
1 = External VCO
0 = Bypass
Make sure that register R0, FCAL_EN is set so that FastLock is enabled.
The loop bandwidth had been design to be around 4 kHz, while phase margin is about 40 degrees.
8.2.2.3 PLL Duplex Mode Application Curves
Figure 73. F1 to F2 Switching
Figure 74. F2 to F1 Switching
Figure 75. F1 to F2 Switching Time
Figure 76. F2 to F1 Switching Time
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