LMH6654 Datasheet, PDF (7/31 Pages) National Semiconductor (TI) – Single/Dual Low Power, 250 MHz, Low Noise Amplifiers

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LMH6654, LMH6655
SNOS956E – JUNE 2001 – REVISED AUGUST 2014
6.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V⁺ = +5V, V^− = −0V, V_CM = 2.5V, A_V = +1, R_F = 25 Ω for gain = +1,
R_F = 402Ω for gain ≥ +2, and R_L = 100Ω to V⁺/2. Boldface limits apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
MIN ⁽¹⁾
TYP ⁽²⁾
MAX ⁽¹⁾
UNIT
DYNAMIC PERFORMANCE
f_CL
Close Loop Bandwidth
GBWP
φm
SR
t_S
Gain Bandwidth Product
Bandwidth for 0.1 dB Flatness
Phase Margin
Slew Rate ⁽³⁾
Settling Time
0.01%
0.1%
A_V = +1
A_V = +2
A_V = +5
A_V = +10
A_V ≥ +5
A_V = +1
A_V = +1, V_IN = 2 V_PP
A_V = +1, 2V Step
230
120
MHz
50
25
250
MHz
17
MHz
48
deg
190
V/µs
30
ns
20
ns
t_r
Rise Time
t_f
Fall Time
DISTORTION and NOISE RESPONSE
A_V = +1, 0.2V Step
A_V = +1, 0.2V Step
1.5
ns
1.35
ns
e_n
Input Referred Voltage Noise
i_n
Input Referred Current Noise
Second Harmonic Distortion
Third Harmonic Distortion
X_t
Crosstalk (for LMH6655 only)
INPUT CHARACTERISTICS
f ≥ 0.1 MHz
f ≥ 0.1 MHz
A_V = +1, f = 5 MHz
V_O = 2 V_PP, R_L = 100Ω
Input Referred, 5 MHz
4.5
nV/√Hz
1.7
pA/√Hz
−65
dBc
−70
−78
dB
V_OS
TC V_OS
I_B
Input Offset Voltage
Input Offset Average Drift
Input Bias Current
V_CM = 2.5V
V_CM = 2.5V ⁽⁴⁾
V_CM = 2.5V
−5
−6.5
±2
5
6.5
mV
6
µV/°C
6
12
18
µA
I_OS
Input Offset Current
V_CM = 2.5V
−2
−3
0.5
2
3
µA
R_IN
Input Resistance
Common Mode
Differential Mode
4
MΩ
20
kΩ
C_IN
Input Capacitance
Common Mode
Differential Mode
1.8
pF
1
CMRR
CMVR
Common Mode Rejection Ration
Input Common Mode Voltage Range
Input Referred,
V_CM = 0V to −2.5V
CMRR ≥ 50 dB
70
68
90
−0.15
3.5
3.7
dB
0
V
TRANSFER CHARACTERISTICS
A_VOL
Large Signal Voltage Gain
V_O = 1.6 V_PP, R_L = 100Ω
58
55
64
dB
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in V_OS at temperature extremes into the total temperature change.
Copyright © 2001–2014, Texas Instruments Incorporated
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