LMC6484 Datasheet, PDF (7/45 Pages) National Semiconductor (TI) – CMOS Quad Rail-to-Rail Input and Output Operational Amplifier

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LMC6484
SNOS675C – AUGUST 2000 – REVISED SEPTEMBER 2015
6.6 DC Electrical Characteristics for LMC6484I
Unless otherwise specified, all limits specified for T_J = 25°C, V⁺ = 5 V, V^− = 0 V, V_CM = V_O = V⁺/2 and R_L > 1 M.
PARAMETER
TEST CONDITIONS
MIN ⁽¹⁾
TYP ⁽²⁾
MAX ⁽¹⁾
V_OS
Input offset voltage
At the temperature extremes
0.11
3
3.7
TCV_OS
Input offset voltage
average drift
1
I_B
Input current⁽³⁾
At the temperature extremes
0.02
4
I_OS
Input offset
current ⁽³⁾
At the temperature extremes
0.01
2
C_IN
Common-mode
input capacitance
3
R_IN
Input resistance
CMRR
Common-mode
rejection ratio
0 V ≤ V_CM ≤ 15 V
V⁺ = 15 V
0 V ≤ V_CM ≤ 5 V
V⁺ = 5 V
At the temperature extremes
At the temperature extremes
>10
65
82
62
65
82
60
+PSRR
Positive power
supply rejection ratio
5 V ≤ V⁺ ≤ 15 V
V^− = 0 V, V_O = 2.5 V
At the temperature extremes
65
62
82
−PSRR
Negative power
supply rejection ratio
−5 V ≤ V^− ≤ −15 V
V⁺ = 0 V, V_O = −2.5
V
At the temperature extremes
65
62
82
V^− − 0.3
−0.25
V_CM
Input common-mode V⁺ = 5 V and 15 V ^{At the temperature extremes}
voltage range
For CMRR ≥ 50 dB
V⁺ + 0.25
V⁺ + 0.3
0
At the temperature extremes
V⁺
120
666
R_L = 2 kΩ ⁽⁴⁾
Sourcing
At the
temperature
extremes
72
35
75
A_V
Large signal voltage
gain
Sinking
At the
temperature
extremes
20
50
300
R_L = 600 Ω ^{(3) (4)}
Sourcing
At the
temperature
extremes
30
15
35
Sinking
At the
temperature
10
extremes
UNIT
mV
µV/˚C
pA
pA
pF
Tera Ω
dB
dB
dB
dB
V
V
V/mV
(1) All limits are specified by testing or statistical analysis.
(2) Typical values represent the most likely parametric normal.
(3) Specified limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
(4) V⁺ = 15 V, V_CM = 7.5 V and R_L connected to 7.5 V. For sourcing tests, 7.5 V ≤ V_O ≤ 11.5 V. For sinking tests, 3.5 V ≤ V_O ≤ 7.5 V.
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