LM3475_14 Datasheet, PDF (7/21 Pages) Texas Instruments – Hysteretic PFET Buck Controller

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Block Diagram
LM3475
SNVS239A – OCTOBER 2004 – REVISED JANUARY 2005
reset
V_IN
en
Pdrive
Internal
Regulator
V_CC
Level
EN
Shift
en
Blanking
Timer
UVD-Disable
-
+
UVD
Comp
Hysteretic
Comp
+
-
Band Gap
Reference
70% V_REF
V_REF
UVD-Disable
Current
Bias
reset
Vref Ramp
Soft-Start
PGATE
FB
GND
OPERATION DESCRIPTION
OVERVIEW
The LM3475 is a buck (step-down) DC-DC controller that uses a hysteretic control architecture, which results in
Pulse Frequency Modulated (PFM) regulation. The hysteretic control scheme does not utilize an internal
oscillator. Switching frequency depends on external components and operating conditions. Operating frequency
decreases at light loads, resulting in excellent efficiency compared to PWM architectures. Because switching is
directly controlled by the output conditions, hysteretic control provides exceptional load transient response.
HYSTERETIC CONTROL CIRCUIT
The LM3475 uses a comparator-based voltage control loop. The voltage on the feedback pin is compared to a
0.8V reference with 21mV of hysteresis. When the FB input to the comparator falls below the reference voltage,
the output of the comparator goes low. This results in the driver output, PGATE, pulling the gate of the PFET low
and turning on the PFET.
With the PFET on, the input supply charges C_OUT and supplies current to the load through the PFET and the
inductor. Current through the inductor ramps up linearly, and the output voltage increases. As the FB voltage
reaches the upper threshold (reference voltage plus hysteresis) the output of the comparator goes high, and the
PGATE turns the PFET off. When the PFET turns off, the catch diode turns on, and the current through the
inductor ramps down. As the output voltage falls below the reference voltage, the cycle repeats. The resulting
output, inductor current, and switch node waveforms are shown in Figure 12.
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: LM3475
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