LM3475_14 Datasheet, PDF (11/21 Pages) Texas Instruments – Hysteretic PFET Buck Controller

LM3475
www.ti.com
SNVS239A – OCTOBER 2004 – REVISED JANUARY 2005
OUTPUT CAPACITOR SELECTION
Once the desired operating frequency and inductance value are selected, ESR must be selected based on
Equation 4. This process may involve a few iterations to select standard ESR and inductance values.
In general, the ESR of the output capacitor and the inductor ripple current create the output ripple of the
regulator. However, the comparator hysteresis sets the first order value of this ripple. Therefore, as ESR and
ripple current vary, operating frequency must also vary to keep the output ripple voltage regulated. The hysteretic
control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low
ESR, resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and
increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output
capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance
provide highly accurate control over the output voltage ripple. Another method is to add an external ramp at the
FB pin as shown in Figure 14. By proper selection of R1 and C2, the FB pin sees faster voltage change than the
output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The
switching frequency is approximately:
V_IN
F=
2S x R₁ x C₂ x V_HYS
(9)
Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended
and may be used without additional series resistance. For all practical purposes, any type of output capacitor
may be used with proper circuit verification.
Capacitors with high ESL (equivalent series inductance) values should not be used. As shown in Figure 12, the
output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly
proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step
large enough to cause abnormal switching behavior.
INPUT CAPACITOR SELECTION
A bypass capacitor is required between V_IN and ground. It must be placed near the source of the external PFET.
The input capacitor prevents large voltage transients at the input and provides the instantaneous current when
the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current
rating. Follow the manufacturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can
be calculated with the equations below:
I_OUT
I_{RMS_CIN} = _VIN
V_OUT x (V_IN - V_OUT)
(10)
V_IN
C_IN
10 PF
Q1
Si2343
5
D1
PGATE
4
2
V_IN
GND
LM3475
3
EN
1
FB
L1
10 PH
C_OUT
100 PF
R1
200k
C1
3.9 nF
C2
390 pF
V_OUT = 0.9V/2A
R_FB1
1.27k
R_FB2
10k
Figure 14. External Ramp
Copyright © 2004–2005, Texas Instruments Incorporated
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